This invention relates to a method of converting an analog input signal into a digital output signal comprising the steps of deriving a square wave duty cycle modulated by the analog input signal, of generating a clock synchronous sampling pulse and of sampling the duty cycle modulated square wave with the clock synchronous sampling pulse to generate the digital output signal.
An arrangement for carrying out such method has been proposed in applicant's earlier european patent application (PHN 16308). This patent application discloses an asynchronous sigma delta modulator as a preferred means for deriving the square wave, which is duty cycle modulated by the analog input signal. The asynchronous sigma delta modulator mainly comprises an integrating filter and a comparator in feedback arrangement, and is relatively easy to build and robust in operation. The square wave, generated by the asynchronous sigma delta modulator, contains the information in the analog time-positions of its transients. In order to convert the signal into a digital format, the square wave is subsequently sampled by a clock synchronous sampling pulse. The sampling of the square wave results in a digital signal which may be referred to as a one-bit-coded bitstream. It is further disclosed in the above mentioned european patent application that the bitstream may be converted in any suitable PCM-format by means of a decimating digital filter.
The process of sampling the duty cycle modulated square wave implies the introduction of sampling noise whose level is lower the higher the sampling rate is. In practice, when usual moving picture video signals have to be converted, a sufficiently low sampling noise is obtained when the sampling rate, and consequently the communication rate between the sampler and the decimating digital filter, is higher then several Gbits/s. Such a high communication rate may pose a serious problem, for instance when the sampler and the decimating filter have to be implemented on different integrated circuits. However, also when sampler and decimating digital filter are implemented on a single integrated circuit, the transport of the bits between the two functional blocks at this high rate may be impractical. The above mentioned european patent application discloses the use of a polyphase sampler using a plurality of samplers, thereby reducing the sampling rate of each individual sampler. However, this measure does not reduce the total communication rate of the bits originating from the entirety of samplers.